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    VLSI - Essential concepts and detailed interview guide

    BY
    Udemy

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    Mode

    Online

    Fees

    ₹ 549 2499

    Quick Facts

    particular details
    Medium of instructions English
    Mode of learning Self study
    Mode of Delivery Video and Text Based

    Course and certificate fees

    Fees information
    ₹ 549  ₹2,499
    certificate availability

    Yes

    certificate providing authority

    Udemy

    The syllabus

    Physical Design Flow Overview

    • Floor- Planning Steps
    • Netlist Binding And Placement Optimization
    • Clock Net Shielding
    • Route - DRC Clean - Parasitics Extraction - Final STA

    Floorplanning

    • Utilization Factor And Aspect Ratio
    • Concept of Pre-placed Cells
    • Power Planning
    • Pin Placement And Logical Cell Placement Blockage

    Placement

    • Netlist Binding And Placement
    • Optimize Placement Using Estimated Wire Length And Capacitance
    • Optimize Placement Continued

    Timing Analysis With Ideal Clocks

    • Setup Time Analysis And Introduction To Flip-Flop Setup Time
    • Setup Timing Analysis With Multiple Clocks
    • Multiple Clock Timing Analysis And Introduction To Data Slew Check
    • Data Slew Check

    Clock Tree Synthesis- Introduction and Quality Check Parameters

    • Introduction To Clock Tree Synthesis
    • Duty Cycle And Latency Check
    • Latency And Power Check
    • Power And Crosstalk Quality Check
    • Glitch Quality Check

    H-Tree

    • H-Tree Algorithm And Skew Check
    • H-Tree Pulse Width And Duty Cycle Check
    • H-Tree Latency And Power Check

    Clock Tree Modelling and Observations

    • Clock Tree Modelling
    • Clock Tree Building
    • Clock Tree Observations

    Buffered H-Tree

    • H-Tree Buffering Observations
    • H-Tree Pulse Width Check And Issues With Regular Buffers
    • CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
    • H-Tree Clock Buffers And Pulse Width Check
    • Dynamic Power And Short Circuit Power

    Clock Tree Optimization Checklist

    • Optimization Checklist
    • Leakage Current Reduction Technique
    • Optimized Clock Tree Power And Latency Check

    Static Timing Analysis With Real Clocks

    • Static Timing Analysis With Real Clocks
    • Impact Of Unbalanced Skew On Setup Time
    • Impact Of Unbalanced Skew On Hold Time

    Introduction to Crosstalk - Why and How Crosstalk occurs in a CHIP??

    • Introduction
    • Dominant Lateral Capacitance
    • Noise Margin Voltage Parameters
    • Lower Supply Voltage

    Glitch Example and Factors Affecting Glitch Height

    • Basic Crosstalk Glitch Example
    • Glitch Discharge With High Drive Strength PMOS Transistor
    • Factors Affecting Glitch Height - Aggressor Drive Strength
    • Factors Affecting Glitch Height - Conclusion

    Tolerable Glitch Heights and Introduction to AC Noise Margin

    • Impacts Of Glitch
    • Tolerable Glitch Heights Using DC Noise Margin
    • AC Noise Margin
    • Justification Of Load Impact And Conclusion

    Crosstalk Delta Delay Analysis

    • Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
    • Setup Timing Analysis Using Real Clocks
    • Crosstalk Delta Delay - Aggressor Victim Switching In Same Direction
    • Impact Of Crosstalk Delta Delay On Hold Timing

    Noise Protection Technique

    • Shielding
    • Spacing
    • Drive Strength

    Routing and Design Rule Check (DRC)

    • Introduction To Maze Routing - Lee's Algorithm
    • Design Rule Check

    Parasitics Extraction

    • Introduction To IEEE 1481-1999 SPEF Format
    • SPEF Header Description, Physical Design Flow Conclusion And What Next !!

    Generated Clock Definition and Creation

    • DEFINE GENERATED CLOCK FOR DIVIDE-BY-2 CIRCUIT
    • GENERATED CLOCKS USING MASTER CLOCK EDGES
    • GENERATED CLOCK WAVEFORM DERIVATION
    • GENERATED CLOCK WITH SHIFTED EDGE

    Basics of mos Transistor

    • INTRODUCTION TO VLSI ACADEMY
    • GATE VOLTAGE AND ACCUMULATION OF NEGATIVE CHARGE
    • N-CHANNEL FORMATION BETWEEN SOURCE AND DRAIN
    • IMPACT OF SUBSTRATE POTENTIAL ON THRESHOLD VOLTAGE (VT)

    SETUP & HOLD TIMING ANALYSIS

    • INITIAL TIMING ANALYSIS AND INTRODUCTION TO FLOP SETUP TIME
    • SETUP TIMING ANALYSIS WITH JITTER AND REAL CLOCKS
    • INTRODUCTION TO SLACK AND HOLD TIMING ANALYSIS
    • HOLD TIMING ANALYSIS CONCLUDED

    Instructors

    Mr Kunal Ghosh

    Mr Kunal Ghosh
    Director, instructors
    Freelancer

    M.E /M.Tech.

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