UPES B.Tech Admissions 2025
ApplyRanked #42 among Engineering colleges in India by NIRF | Highest CTC 50 LPA , 100% Placements
Exam GATE | Seats 18 |
MODE
Full timeDURATION
24 MonthsMaster of Engineering (ME) in VlSI Design and Embedded Systems is a two-year full-time postgraduate Course offered by Sinhgad College of Engineering, Pune recognized by All India Council for Technical Education (AICTE) and affiliated to Savitribai Phule Pune University, Pune.
Exams and Events | Dates |
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GATE Application Date (Mode - Online) | 23 Aug'24 - 25 Sep'24 |
GATE Late Fee Application Date (Mode - Online) | 26 Sep'24 - 6 Oct'24 |
GATE Score Card Date - Score cards available for download by paying a fee of Rs. 500 per test paper (Mode - Online) | 31 May'24 - 30 Dec'24 |
GATE Exam Date (Mode - Online) | 31 Jan'25 - 1 Feb'25 |
GATE Exam Date (Mode - Online) | 14 Feb'25 - 15 Feb'25 |
Eligibility criteria for Maharashtra State Candidate:
All the specialization wise admission to the AICTE approved two years Master Degree course in Engineering in the state of Maharashtra for the academic year onwards shall be done on the basis of Non – Zero GATE score only. No specialization wise entrance examination for ME admission for the academic year be conducted by the Directorate of Technical Education, Maharashtra State.
Ranked #42 among Engineering colleges in India by NIRF | Highest CTC 50 LPA , 100% Placements
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