Circuit Design for High Speed Serial Links

BY
Udemy

Mode

Online

Fees

₹ 1799

Quick Facts

particular details
Medium of instructions English
Mode of learning Self study
Mode of Delivery Video and Text Based

Course and certificate fees

Fees information
₹ 1,799
certificate availability

Yes

certificate providing authority

Udemy

The syllabus

Introduction

  • Introduction

Job Oriented Course Sections - IMPORTANT

  • Job Oriented Course Sections

Need for High Speed Links

  • Need for Large Data transport
  • Why Serial Links?
  • Deserializer for Transceivers

Circuits for High Speed Links

  • HSL Overview
  • Transmission Line Gain and Reflection with example
  • Cascode Circuits - For High gain in TX Driver and CTLE
  • Cascode Circuits - Shielding and Node Isolation
  • Knowledge of Clocked Latches

Transmitter Architecture

  • Basic Circuits for TX and RX: Latch MUX and DeMUX for high speed I/O
  • Serializer and Deserializer Design - Target of 20Gbps data rate

Receiver Architecture Design parameters

  • How to decide the receiver architecture design
  • Quick Quiz

Continuous Time Linear Equalizer

  • Continuous Time Linear Equalizer (CTLE)
  • Question: When and where will I need a CTLE ?
  • Question: Is CTLE needed for an Receiver in FPGA

Major Blocks of HSL

  • Clocking Solutions overview
  • Phase Locked Loop (PLL)

Quiz

  • Final Quiz

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