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Quick Facts

Medium Of InstructionsMode Of LearningMode Of Delivery
EnglishSelf StudyVideo and Text Based

Important dates

Course Commencement Date

Start Date : 20 Jan, 2025

End Date : 11 Apr, 2025

Certificate Exam Date

Start Date : 27 Apr, 2025

Enrollment Date

Tentative Date : 27 Jan, 2025

Other

End Date : 14 Feb, 2025

Courses and Certificate Fees

Fees InformationsCertificate AvailabilityCertificate Providing Authority
INR 1000yesIIT Guwahati (IITG)

The Syllabus

  • Lecture 1: Introduction to Digital Design
  • Lecture 2: Switching Algebra
  • Lecture 3: Number Systems

  • Lecture 4: Number Systems: Conversion of Bases
  • Lecture 5: Number Systems: Sign representation,
  • Lecture 6: 2's complement addition
  • Lecture 7: Binary Codes

  • Lecture 8: Minimization of Boolean functions: Karnaugh Map
  • Lecture 9: Prime Implicants and Essential Prime Implicants
  • Lecture 10: Tabulation method
  • Lecture 11: Prime implicant chart and its reduction, Branching method

  • Lecture 12: ESPRESSO: Heuristic-based Logic Optimization
  • Lecture 13: Prime Implicants and Essential Prime Implicants
  • Lecture 14: Multi-level Logic Minimization using Prime Implication Chart

  • Lecture 15: Verilog(Cont)
  • Lecture 16: Verilog(Cont)
  • Lecture 17: Verilog

  • Lecture 18: Code Conversion, Parity Checker, Comparator
  • Lecture 19: Multiplexer, Decoder Decimal Decoder,
  • Lecture 20: Full-Adder, Ripple Carry Adder

  • Lecture 21: Carry Look ahead adder
  • Lecture 22: Sign adder, Add/Sub,
  • Lecture 23: BCD Adder, Multiplier
  • Lecture 24: Combinational Design using Verilog
  • Lecture 25: Combinational Design using Verilog

  • Lecture 26: Sequential Design: Flipflop
  • Lecture 27: Sequential Design: Counter
  • Lecture 28: Sequential Design: Register

  • Lecture 29: Implementation of FLipflop,
  • Lecture 30: counters and registers in Verilog
  • Lecture 31: Finite State Machine Modeling Sequential Design with FSM
  • Lecture 32: Implementation Methodologies for FSM FSM Minimization

  • Lecture 33: Implementation of FSM using Verilog
  • Lecture 34: Implementation of FSM using Verilog
  • Lecture 35: Implementation of FSM using Verilog
  • Lecture 36: Testing of FSM

  • Lecture 37: Algorithmic State Machine and RTL
  • Lecture 38: Implementation Methodologies for ASM
  • Lecture 39: RTL design of Sequential Multiplier using ASM/RTL

  • Lecture 40: RTL Design using Verilog(Cont)
  • Lecture 41: RTL Design using Verilog(Cont)
  • Lecture 42: RTL Design using Verilog

Instructors

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