Search Colleges, Exams, Schools & more
Interested in this College?
Get updates on Eligibility, Admission, Placements Fees Structure
CompareGet updates on Eligibility, Admission, Placements Fees Structure
Quick Facts
| Medium Of Instructions | Mode Of Learning | Mode Of Delivery |
|---|---|---|
| English | Self Study | Video and Text Based |
Courses and Certificate Fees
| Fees Informations | Certificate Availability | Certificate Providing Authority |
|---|---|---|
| INR 1000 | yes | IIT Guwahati (IITG) |
The Syllabus
Basic Computer Organization
- Review of Basic Computer Organization
- Basic operational concepts
- Fundamental of program execution
- Memory and I/O addressing
- Instruction set architecture- addressing modes, instruction set, instruction encoding and formats
- CISC vs RISC ISA
Instruction Pipeline Principles
- Performance Evaluation Methods
- Introduction to RISC Instruction Pipeline
- Instruction Pipeline and Performance
- Pipeline Hazards and Analysis
Pipeline Hazards and Branch Prediction Techniques
- Pipeline Hazards Management Techniques
- Branch Prediction
- MIPS Pipeline for Multi-Cycle Operations
Pipeline Scheduling and Speculative Execution
- Compiler Techniques to Explore Instruction Level Parallelism
- Dynamic Scheduling with Tomasulo’s Algorithm
- Speculative Execution
Superscalar Processors and GPU architectures
- Advanced Pipelining
- Multithreading and Hyperthreading
- Superscalar Processors
- GPU Architectures
Cache Memory Principles
- Introduction to Cache Memory
- Block Replacement Techniques and Write Strategy
- Design Concepts in Cache Memory
Cache Memory Optimizations
- Design issues for improving memory access time
- Basic and Advanced Optimization Techniques in Cache Memory
Cache Coherence Protocols
- Cache coherence and memory consistency
- Snoop Based and Directory Based Cache coherence Protocols
Primary Storage Systems
- Introduction to DRAM System
- DRAM organization
- DRAM Controllers and Address Mapping
Tiled Chip Multi-Core Processors & Network-on-Chip
- Tiled Chip Multicore Processors (TCMP)
- Network on Chips (NoC)
- Routing Algorithms
- NoC router – architecture
- Routing and flow control
Energy Efficient NoCs
- Introduction to deflection routing
- Energy Efficient Buffer-less NoC Routers
- Side-buffered Deflection Routers
Quality of Service for TCMPs
- QoS of NoC and Caches in TCMPs
- Emerging Trends in Network On Chips
- Domain Specific Accelerators
Instructors
Articles
19 Dec'24, 09:48 AM
19 Dec'24, 06:44 AM
17 Dec'24, 12:40 PM
17 Dec'24, 04:01 AM
17 Dec'24, 03:43 AM
16 Dec'24, 12:25 PM
16 Dec'24, 11:46 AM
13 Dec'24, 12:28 PM
13 Dec'24, 09:28 AM
6 Dec'24, 04:30 AM
4 Dec'24, 03:15 AM
29 Nov'24, 06:03 AM
19 Nov'24, 10:59 AM
2 Nov'24, 06:52 AM
11 Oct'24, 06:01 AM
13 Mar'24, 06:24 AM
29 Feb'24, 06:05 AM
27 Feb'24, 10:32 AM
13 Feb'24, 06:25 AM
19 Dec'24, 09:48 AM
19 Dec'24, 06:44 AM
17 Dec'24, 12:40 PM
17 Dec'24, 04:01 AM
17 Dec'24, 03:43 AM
16 Dec'24, 12:25 PM
16 Dec'24, 11:46 AM
13 Dec'24, 12:28 PM
13 Dec'24, 09:28 AM
Back to top