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Quick Facts

Medium Of InstructionsMode Of LearningMode Of Delivery
EnglishSelf StudyVideo and Text Based

Important dates

Course Commencement Date

Start Date : 20 Jan, 2025

End Date : 11 Apr, 2025

Enrollment Date

End Date : 27 Jan, 2025

Certificate Exam Date

Start Date : 27 Apr, 2025

Other

End Date : 14 Feb, 2025

Courses and Certificate Fees

Fees InformationsCertificate AvailabilityCertificate Providing Authority
INR 1000yesIIT Kharagpur

The Syllabus

  • Importance
  • Challenges
  • Levels of abstraction
  • Fault Models
  • Advanced issues
  • Importance
  • Challenges
  • Levels of abstraction
  • Fault Models
  • Advanced issues
  • Importance
  • Challenges
  • Levels of abstraction
  • Fault Models
  • Advanced issues

  • Introduction
  • Testability Analysis
  • DFT Basics
  • Scan cell design 
  • Scan Architecture
  • Introduction
  • Testability Analysis
  • DFT Basics
  • Scan cell design 
  • Scan Architecture
  • Introduction
  • Testability Analysis
  • DFT Basics
  • Scan cell design 
  • Scan Architecture

  • Scan design rules
  • Scan design flow
  • Fault Simulation: Introduction, Simulation models
  • Scan design rules
  • Scan design flow
  • Fault Simulation: Introduction, Simulation models
  • Scan design rules
  • Scan design flow
  • Fault Simulation: Introduction, Simulation models

  • Logic simulation
  • Fault simulation
  • Logic simulation
  • Fault simulation
  • Logic simulation
  • Fault simulation

  • Introduction
  • Exhaustive testing
  • Boolean difference
  • Basic ATPG algorithms
  • Introduction
  • Exhaustive testing
  • Boolean difference
  • Basic ATPG algorithms
  • Introduction
  • Exhaustive testing
  • Boolean difference
  • Basic ATPG algorithms

  • ATPG for non stuck-at faults
  • Other issues in test generation Built-In-Self-Test: Introduction 
  • BIST design rules
  • ATPG for non stuck-at faults
  • Other issues in test generation Built-In-Self-Test: Introduction 
  • BIST design rules
  • ATPG for non stuck-at faults
  • Other issues in test generation Built-In-Self-Test: Introduction 
  • BIST design rules

  • Test pattern generation
  • Output response analysis
  • Logic BIST architectures
  • Test pattern generation
  • Output response analysis
  • Logic BIST architectures
  • Test pattern generation
  • Output response analysis
  • Logic BIST architectures

  • Introduction
  • Stimulus compression
  • Introduction
  • Stimulus compression
  • Introduction
  • Stimulus compression

  • Stimulus compression
  • Response compression
  • Stimulus compression
  • Response compression
  • Stimulus compression
  • Response compression

  • Introduction
  • RAM fault models
  • RAM test generation
  • Introduction
  • RAM fault models
  • RAM test generation
  • Introduction
  • RAM fault models
  • RAM test generation

  • Memory BIST Power and Thermal Aware Test: Importance, Power models, Low power ATPG
  • Memory BIST Power and Thermal Aware Test: Importance, Power models, Low power ATPG
  • Memory BIST Power and Thermal Aware Test: Importance, Power models, Low power ATPG

  • Low power BIST
  • Thermal aware techniques
  • Low power BIST
  • Thermal aware techniques
  • Low power BIST
  • Thermal aware techniques

Instructors

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