Integral University B.Tech Admissions 2024
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Quick Facts
Total Fees 1.58 L | Exam GATE | Seats 22 |
Fees Details
General
₹ 1.58 L
Disclaimer: Data for total fees has been calculated based on all years/semesters as provided by the college. The actual fees may vary.
Course Details
MODE
Full timeDURATION
24 MonthsMaster of Technology (M.Tech) in VLSI Design and Embedded System under the Department of Electronics and Communication Engineering is a two-year (4 Semesters)full-time postgraduate program offered by National Institute of Technology Arunachal Pradesh.
Important dates
| Exams and Events | Dates |
|---|
GATE Application Correction Date (Mode - Online) | 7 Oct'24 - 5 Nov'24 |
GATE Score Card Date - Score cards available for download by paying a fee of Rs. 500 per test paper (Mode - Online) | 31 May'24 - 30 Dec'24 |
GATE Admit Card Date (Mode - Online) | 1 Jan'25 - 1 Jan'25 |
GATE Exam Date (Mode - Online) | 31 Jan'25 - 1 Feb'25 |
GATE Exam Date (Mode - Online) | 14 Feb'25 - 15 Feb'25 |
GATE Result Date (Mode - Online) | 18 Mar'25 - 18 Mar'25 |
GATE Score Card Date (Mode - Online) | 27 Mar'25 - 30 May'25 |
GATE Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online) | 31 May'25 - 30 Dec'25 |
Eligibility Criteria
Minimum CGPA of 6.5 or 60% of marks or First Class in the qualifying degree, fulfilling specific requirements for different disciplines, as indicated below.
VLSI and Embedded Systems: Bachelor ’s degree in Electronics & Communication Engineering/Computer Science & Engineering or Equivalent or MSc(Electronics) and a valid GATE score in Electronics & Communication, Computer Science & Information Technology or Physics.
Admission Details
Admission to all categories of students is granted on the basis of GATE Score/ counseling/interview/admission test held usually during the month of May -July every year.
Top Exams Accepted by NIT Arunachal Pradesh
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