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Quick Facts

Medium Of InstructionsMode Of LearningMode Of Delivery
EnglishSelf StudyVideo and Text Based

Courses and Certificate Fees

Fees InformationsCertificate AvailabilityCertificate Providing Authority
INR 2436yesCoursera

The fees for the course FPGA computing systems: Partial Dynamic Reconfiguration is -

HeadAmount in INR
Certificate FeesRs. 2,436

 


The Syllabus

Videos
  • Course Introduction
  • A Common Vocabulary
  • The 5 W's
  • Reconfigurable Computing As An Exstension Of Hw/Sw Codesing
  • A Classification Of Soc Reconfigurations
  • A Classification Of Somc Reconfigurations
Readings
  • Design Methodology For Partial Dynamic Reconfiguration: A New Degree Of Freedom In The Hw/Sw Codesign [Suggested Readings]
  • Performance Of Partial Reconfiguration In Fpga Systems: A Survey And A Cost Model [Suggested Readings]
Assignments
  • Functionalities And Their Implementations
  • Module Review

Videos
  • Scenarios Where Partial Reconfiguration Can Be Effective
  • How To Use Fpga Reconfiguration To Face Area Issues
  • How To Deal With The Reconfiguration Runtime Overhead
  • Recurring Modules To Reuse Them To Reduce The Reconfiguration Time
  • Partial Reconfiguration To Reduce The Reconfiguration Runtime Overhead
  • Runtime Management To Explore Alternative Implementations
  • Bitstreams Relocation
  • Bitstreams Relocation And Virtual Homogeneity
Readings
  • Operating System Runtime Management Of Partially Dynamically Reconfigurable Embedded Systems [Suggested Readings]
  • Core Allocation And Relocation Management For A Self Dynamically Reconfigurable Architecture [Suggested Readings]
  • A Runtime Relocation Based Workflow For Self Dynamic Reconfigurable Systems Design [Suggested Readings]
  • Partial Dynamic Reconfiguration In A Multi-Fpga Clustered Architecture Based On Linux [Suggested Readings]
Assignments
  • Reconfigurable System
  • Partial Reconfiguration

Videos
  • Xilnx Design Flows Through Years
  • Partial Reconfiguration Design Flows
  • Xilinx Difference Based Partial Reconfiguration
  • Xilinx Module Based Partial Reconfiguration
  • Xilinx Partial Reconfiguration (Pr) Flow
  • Module Based Vs Partial Reconfiguration Design Flows
  • Rationale Behind Dresd And The Work Done By The Politecnico Di Milano
  • From Dresd To Change And Asap, Two New Research Initiatives From The Politecnico Di Milano
  • Caos: From Embedded To Heterogeneous Distributed Fpga-Based Computing Systems
Readings
  • Vivado Design Suite Tutorial, Partial Reconfiguration, Ug947 (V2016.1) April 6, 2016 [Suggested Readings - Handbook - Pdf]
  • Vivado Design Suite User Guide, Partial Reconfiguration, Ug909 (V2016.1) April 6, 2016 [Suggested Readings - Handbook - Pdf]
  • Dynamic Reconfigurability In Embedded System Design [Suggested Readings]
  • A Design Methodology For Dynamic Reconfiguration: The Caronte Architecture [Suggested Readings]
  • Floorplanning Automation For Partial-Reconfigurable Fpgas Via Feasible Placements Generation [Suggested Readings]
  • Heterogeneous Exascale Supercomputing: The Role Of Cad In The Exafpga Project [Suggested Readings]
  • The Role Of Cad Frameworks In Heterogeneous Fpga-Based Cloud Systems [Suggested Readings]
Assignments
  • Abstractions
  • Politecnico Di Milano Partial Reconfiguration Research Initiatives
  • Design Flows

Videos
  • Towards Distributed Fpga-Based Systems
Readings
  • Virtualized Execution Runtime For Fpga Accelerators In The Cloud [Suggested Readings]
  • A Cloud-Scale Acceleration Architecture [Suggested Readings]
  • Enabling Flexible Network Fpga Clusters In A Heterogeneous Cloud Data Center [Suggested Readings]
  • Conclusion
Assignments
  • Closing Remarks And Future Directions

Instructors

Articles

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