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Quick Facts
| Medium Of Instructions | Mode Of Learning | Mode Of Delivery |
|---|---|---|
| English | Self Study | Video and Text Based |
Course Overview
The Hardware Description Languages for FPGA Design course by Coursera has been conceptualized in a way to enable the learners to get an insight into Hardware Description Languages for Logic Design and work towards their career in that direction. This course will give candidates an extensive introduction of the VHDL and Verilog which are the most widespread design methods for FPGA Design.
Coursera has collaborated with instructors from world-wide universities and companies. The learners will get access to quizzes, online videos, community discussion forums, and practice exercises.
Coursera in collaboration with the University of Colorado Boulder is providing this course. The natural learning process is utilized to make the learning of the languages easy. In the beginning, only simple examples are presented. The course also covers language rules and syntax and followed by more complex examples.
They will develop the skills required to design circuits using VHDL and Verilog and sufficient knowledge to continue gaining expertise in Verilog and VHDL further. This course is a part of the FPGA Design for Embedded Systems Specialization and can be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
The Highlights
- Flexible deadlines
- 7 days free trial
- Online learning
- Intermediate level course
- Course completion takes approximately 36 hours
- Offered by University of Colorado Boulder
- Subtitles in English, French, Portuguese (Brazilian), Russian, Spanish
Programme Offerings
- Practice Exercises
- Graded Quizzes
- E-learning Videos
- reading resources
- Shareable Certificate.
Courses and Certificate Fees
| Certificate Availability | Certificate Providing Authority |
|---|---|
| yes | CU BoulderCoursera |
Fees payable for the Hardware Description Languages for FPGA Design course by Coursera are:
Rs.6,587 /- monthly for all candidates
Fee details for Hardware Description Languages for FPGA Design course by Coursera
Head | Amount |
1 Month | Rs. 6,634 |
3 Months | Rs. 13,268 |
6 Months | Rs. 19,903 |
Eligibility Criteria
Certification Qualifying Details
If candidates complete the programme and pay for it then they will be able to get the certificate of completion.
What you will learn
After the completion of the Hardware Description Languages for FPGA Design course by Coursera the participants will have a detailed perspective about the following:
- The basic concepts of VHDL language
- Understanding VHDL Assignments, Operators and Types
- Learning the usage of Combinatorial Circuits
- Learning how to evaluate Verilog
- Understanding the Verilog Modules, Port Modes and Data Types
- Expertise in designing test benches
Who it is for
Application Details
Candidates who look forward to enrolling for the Hardware Description Languages for FPGA Design course by Coursera can follow the given steps:
Step1: Visit the course page and click on Enroll for Free Tab.
Step 2: Sign up and access the free 7-day trial version.
Step 3: Once the trial version ends, simply purchase the programme.
Step 4: Payment can be made as per the desired payment mode.
The Syllabus
Videos
- Introduction to Hardware Description Languages for FPGA Design
- Why Learn VHDL?
- FPGA Design Flow
- Intro to VHDL: Finite State Machine
- How to speak VHDL, first phrases
- VHDL Assignments, Operators, Types
- VHDL Rules and Syntax, Interface Ports
- VHDL in ModelSim: Download and Install
- VHDL in ModelSim: Adding to your Toolkit
- Submitting VHDL Programming Assignments
Readings
- Hardware Description Languages for FPGA Design Assessment Strategy
- Misson 2-001: Week 1 Readings
- Files for Week 1 Programming Assignments
Quiz
- VHDL Find the Code Errors
- Module 1 Quiz
Videos
- Learning to speak VHDL (Intro)
- Combinatorial Circuits
- Synchronous Logic: Latches and Flip Flops
- Synchronous Logic: Counters and Registers
- Buses and Tristate Buffers
- Modular Designs: Components, Generate and Loops in VHDL
- Test Benches in VHDL: Combinatorial
- Test Benches in VHDL: Synchronous
- Memory in VHDL
- Finite State Machines in VHDL
Readings
- Week 2 Readings
- Files for Week 2 Programming Assignments
Quiz
- Module 2 Quiz
Videos
- Verilog for fun and profit (Intro)
- Your First Verilog phrase
- Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing
- Verilog Statements and Operators
- Verilog Modules, Port Modes and Data Types
- Verilog Structure
- Testing with ModelSim
- Verilog Evaluation
- Submitting Verilog Programming Assignments
Readings
- Week 3 Readings
- Files for Week 3 Programming Assignments
Quiz
- Verilog Find the Errors
- Module 3 Quiz
Videos
- Learning to speak Verilog (Intro)
- Combinatorial Circuits
- Synchronous Logic: Latches and Flip Flops
- Synchronous Logic: Counters and Registers
- Buses and Tristate Buffers
- Modular Design in Verilog
- Testbenches in Verilog
- Testbenches in Verilog II
- Memory with Verilog
- Verilog Finite State Machines
Readings
- Week 4 Readings
- Files for Week 4 Programming Assignments
Quiz
- Module 4 Quiz
Instructors
CU Boulder Frequently Asked Questions (FAQ's)
If the participants have any doubt or question regarding something they learned in the course, they can post it in the discussion forum. Other learners or course mentors will respond to the posts.
If the participants only wish to read and view the course content, they can take audit access to the course. The access is given for free by Coursera.
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Course completion certificate URL can be included on CVs, resumes, or other documents. Coursera provides a secure Coursera URL where candidates will get Certificate and course information.