UPES B.Tech Admissions 2025
ApplyRanked #42 among Engineering colleges in India by NIRF | Highest CTC 50 LPA , 100% Placements
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Quick Facts
Exam GATE | Seats 9 |
Course Details
MODE
Full timeDURATION
24 MonthsMaster of Engineering (ME) in VLSI and Embedded Systems is a two-year full-time postgraduate program recognized by the All India Council for Technical Education (AICTE) and offered by the Savitribai Phule Pune University, Pune.
Important dates
| Exams and Events | Dates |
|---|
GATE Score Card Date - Score cards available for download by paying a fee of Rs. 500 per test paper (Mode - Online) | 31 May'24 - 30 Dec'24 |
GATE Admit Card Date (Mode - Online) | 1 Jan'25 - 1 Jan'25 |
GATE Exam Date (Mode - Online) | 31 Jan'25 - 1 Feb'25 |
GATE Exam Date (Mode - Online) | 14 Feb'25 - 15 Feb'25 |
GATE Result Date (Mode - Online) | 18 Mar'25 - 18 Mar'25 |
GATE Score Card Date (Mode - Online) | 27 Mar'25 - 30 May'25 |
GATE Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online) | 31 May'25 - 30 Dec'25 |
Eligibility Criteria
Candidate should have passed/appeared Bachelor degree or equivalent in the relevant field of Engineering/Technology from State Governments/MHRD approved institutions, with at least 50 % Aggregate marks (at least 45% marks in case of candidates of backward class categories and persons with disability belonging to Maharashtra State only).
Admission Details
Having a Positive and valid GATE Score in the respective qualifying branch.
Top Exams Accepted by DY Patil College of Engineering, Pune
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