Chandigarh University Admissions 2025
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Quick Facts
Total Fees 1.54 L | Exam GATE | Seats 9 |
Fees Details
General
₹ 1.54 L
Disclaimer: Data for total fees has been calculated based on all years/semesters as provided by the college. The actual fees may vary.
Course Details
MODE
Full timeDURATION
24 MonthsMaster of Technology (M.Tech) in VLSI and Embedded Systems Design is a two-year full-time postgraduate program recognized by the All India Council for Technical Education (AICTE) and offered by the Dr APJ Abdul Kalam Technical University, Lucknow APJ Abdul Kalam Technical University, Lucknow.
Important dates
| Exams and Events | Dates |
|---|
GATE Admit Card Date (Mode - Online) | 6 Jan'25 - 6 Jan'25 |
GATE Exam Date (Mode - Online) | 31 Jan'25 - 1 Feb'25 |
GATE Exam Date (Mode - Online) | 14 Feb'25 - 15 Feb'25 |
GATE Result Date (Mode - Online) | 18 Mar'25 - 18 Mar'25 |
GATE Score Card Date (Mode - Online) | 27 Mar'25 - 30 May'25 |
GATE Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online) | 31 May'25 - 30 Dec'25 |
Eligibility Criteria
The Candidate should pass B.E /B.Tech. (Minimum 50%* or equivalent in CGPA) in Electronics & Communication Engineering / Electronics Engineering / Electrical & Electronics Engineering / Electronics & Instrumentation Engineering.
Admission Details
- Direct Admission for candidates having valid GATE Scorecard / AKTU PG Entrance Exam qualified.
- Institute Level Test for Non-GATE / Non-AKTU PG Entrance Exam candidates.
Top Exams Accepted by NIELIT Gorakhpur
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