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Quick Facts

Exam
GATE

Course Details

MODE

Full time

DURATION

24 Months

The Department of Electrical Engineering of Shiv Nadar University, Delhi-NCR, offers a full-time MTech program in VLSI Design and Embedded Systems (VLSID-ES). Students are admitted to the semester starting in August (Monsoon semester) for the 2-year program.

Shiv Nadar University’s MTech program is tailored to strengthen the foundations and hands-on experience of students in the fields of VLSI Design and Embedded Systems, with a two-fold objective:

(a) Students become more industry-ready and can hit the ground running

(b) Students get primed to continue doctoral-level research in select areas 


Important dates

Exams and EventsDates
GATE
Application Correction Date (Mode - Online)
30 Oct'24 - 9 Nov'24
GATE
Score Card Date - Score cards available for download by paying a fee of Rs. 500 per test paper (Mode - Online)
31 May'24 - 30 Dec'24
GATE
Admit Card Date (Mode - Online)
1 Jan'25 - 1 Jan'25
GATE
Exam Date (Mode - Online)
31 Jan'25 - 1 Feb'25
GATE
Exam Date (Mode - Online)
14 Feb'25 - 15 Feb'25
GATE
Result Date (Mode - Online)
18 Mar'25 - 18 Mar'25
GATE
Score Card Date (Mode - Online)
27 Mar'25 - 30 May'25
GATE
Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online)
31 May'25 - 30 Dec'25

Eligibility Criteria

Eligibility

  • Candidates should have completed a B.Tech/BE/BS (4 years) in ECE/EE/EEE or equivalent with a minimum 60% score or 6.5 CGPA or an MSc in Physics/Electronics or equivalent with a minimum 60% score or 6.5 CGPA.
  • Candidates with a valid GATE/CUET-PG score (in Electronics/Electrical Engg domains) will be preferred

Selection Process

  • Candidates who meet the eligibility criteria must take a written test, which will be held on dates announced later.
    • GATE-qualified candidates are exempted from the written test.
    • CUET-PG candidates may be exempted from the written test depending on their CUET-PG score.
  • Candidates qualifying for the written test (or those exempted from it) will be called for an interview.
  • Final selections will be based on past academic performance, GATE/CUET-PG scores, a written test (if applicable), and interviews.

Syllabus for the written test

  • Mathematical aptitude, reasoning, and knowledge in core subjects of ECE will be tested. Please refer to the GATE syllabus for Electronics and Communication Engineering (ECE) for details.

Top Exams Accepted by Shiv Nadar University, Greater Noida

Applications for Admissions are open.

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News and Notifications
2 days ago :

From Nov 10- 25, 2024 Shiv Nadar University will host the Sagamore XX Conference of the IUCr Commission.

2 days ago :

Shiv Nadar University, Greater Noida admission open for 2025; apply via the official website.

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