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Quick Facts

Exam
GATE
Seats
18

Course Details

MODE

Full time

DURATION

24 Months

Master of Technology (M.Tech) in VLSI and Embedded System Design is a two-year full-time postgraduate program recognized by the All India Council for Technical Education (AICTE) and offered by the Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal


Important dates

Exams and EventsDates
GATE
Application Date - without late fee (Mode - Online)
27 Aug'24 - 2 Oct'24
GATE
Late Fee Application Date (Mode - Online)
2 Oct'24 - 6 Oct'24
GATE
Application Correction Date (Mode - Online)
7 Oct'24 - 5 Nov'24
GATE
Score Card Date - Score cards available for download by paying a fee of Rs. 500 per test paper (Mode - Online)
31 May'24 - 30 Dec'24
GATE
Admit Card Date (Mode - Online)
1 Jan'25 - 1 Jan'25
GATE
Exam Date (Mode - Online)
31 Jan'25 - 1 Feb'25
GATE
Exam Date (Mode - Online)
14 Feb'25 - 15 Feb'25
GATE
Result Date (Mode - Online)
18 Mar'25 - 18 Mar'25
GATE
Score Card Date (Mode - Online)
27 Mar'25 - 30 May'25
GATE
Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online)
31 May'25 - 30 Dec'25

Eligibility Criteria

  • The candidate has to Completed BE/B Tech in the appropriate Branch.

Admission Details

Admissions are either through the GATE entrance test or are based on qualifying examination marks.

Top Exams Accepted by Vidhyapeeth Institute of Science and Technology, Bhopal

Applications for Admissions are open.

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