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Quick Facts

Total Fees
1.28 L
Exam
GATE
Seats
18

Fees Details

General

1.28 L

Disclaimer: Data for total fees has been calculated based on all years/semesters as provided by the college. The actual fees may vary.

Course Details

MODE

Full time

DURATION

24 Months

Master of Technology in (Electronics & Communication Engineering) VLSI Design is a two-year full-time course offered by Deenbandhu Chhotu Ram University of Science and Technology, Murthal.


Important dates

Exams and EventsDates
GATE
Admit Card Date (Mode - Online)
6 Jan'25 - 6 Jan'25
GATE
Exam Date (Mode - Online)
31 Jan'25 - 1 Feb'25
GATE
Exam Date (Mode - Online)
14 Feb'25 - 15 Feb'25
GATE
Result Date (Mode - Online)
18 Mar'25 - 18 Mar'25
GATE
Score Card Date (Mode - Online)
27 Mar'25 - 30 May'25
GATE
Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online)
31 May'25 - 30 Dec'25

Eligibility Criteria

The candidate should have a degree in B.E./B.Tech or equivalent in Electronics Engineering / Electronics and Instrumentation Control/ Instrumentation and Control/ Electronics and Communication Engg./Electronics and Telecommunication Engg./Electronics Instt. and Control/Electrical and Electronics Engg./ Instrumentation Engg./M.Sc. (Electronics) scoring at least 50% (47.50% for SC/PH) marks in aggregate.

Admission Details

Candidates with valid GATE score need not to appear in the entrance test for M.Tech.

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