UPES B.Tech Admissions 2025
ApplyRanked #42 among Engineering colleges in India by NIRF | Highest CTC 50 LPA , 100% Placements
Total Fees 2.30 L | Exam GATE | Seats 30 |
₹ 2.30 L
MODE
Full timeDURATION
24 MonthsMaster of Technology (M.Tech) in Electronics and Communication Engineering (VLSI Design) is a two-year full-time postgraduate course and it is offered by Indira Gandhi Delhi Technical University for Women, Delhi, and approved by AICTE.
Relaxation in marks for reserved categories:
Exams and Events | Dates |
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GATE Application Correction Date (Mode - Online) | 7 Oct'24 - 5 Nov'24 |
GATE Score Card Date - Score cards available for download by paying a fee of Rs. 500 per test paper (Mode - Online) | 31 May'24 - 30 Dec'24 |
GATE Admit Card Date (Mode - Online) | 1 Jan'25 - 1 Jan'25 |
GATE Exam Date (Mode - Online) | 31 Jan'25 - 1 Feb'25 |
GATE Exam Date (Mode - Online) | 14 Feb'25 - 15 Feb'25 |
GATE Result Date (Mode - Online) | 18 Mar'25 - 18 Mar'25 |
GATE Score Card Date (Mode - Online) | 27 Mar'25 - 30 May'25 |
GATE Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online) | 31 May'25 - 30 Dec'25 |
Minimum 60% or equivalent in the qualifying exam as under:
Note: Candidate appearing in the Final year/semester of their qualifying degree may also apply.
The admission to M.Tech. the course will be on the basis of the valid GATE Score secured by applicants and thereafter on the basis of the marks secured in the qualifying examination, as per the eligibility. The first preference would be given to candidates having valid GATE scores.
Ranked #42 among Engineering colleges in India by NIRF | Highest CTC 50 LPA , 100% Placements
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